The present invention relates to analog to digital converters, and more particularly to an analog to digital converter that utilizes subranging and interpolation in a pipelined architecture that converts analog samples into corresponding digital values.
Analog to digital converters (ADCs) perform a common and basic function that is necessary in many different types of applications. The primary function of an ADC is to convert an analog input signal to a digital value or binary code for use by various circuits and electronic devices. ADCs range in size, complexity, and accuracy or resolution, where each of these factors depend upon the particular needs of the underlying application. An ADC in accordance with the present invention is illustrated for an application that requires a relatively high degree of accuracy and resolution. It is appreciated, however, that although embodiments of the present invention enable such capabilities, the present invention is not limited to any particular types of ADCs or their applications but instead is applicable to any ADC and application regardless of specific requirements.
Embodiments of the present invention may be employed, for example, in a cellular telephone base station in which it is desired to detect and resolve a broad range of signals in a wireless infrastructure. Within a given cell of a cellular infrastructure, different cell phones operate at different power levels and frequencies. The ADC employed at the front end of the base station must be able to digitize the entire bandwidth of operation to service all cellular phones within its cell. The cell phones are mobile and at variable distances from the base station. The base station must be able to resolve the xe2x80x9cnear-farxe2x80x9d issue and detect all signals within the cell regardless of distances and power levels, and must be able to distinguish between strong and relatively weak signals.
It is desired that an ADC employed in a cellular base station application digitize an input analog signal with a very high degree of accuracy. The ADC should exhibit a high degree of linearity, have a relatively high resolution with a high signal to noise ratio (SNR). In the cellular base station application, for example, it is desired that the ADC have a resolution of 14 bits with a spurious free dynamic range (SFDR) of 105 dBc and with an SNR of greater than 75 dB and operate at a Nyquist rate of approximately 80 MHz to accurately represent an input signal with a bandwidth of 40 MHz. Such 14-bit resolution is analogous to being able to distinguish the approximate thickness of a human hair on an 8 foot wall. The requisite SFDR enables determination of whether the variation of the thickness of the hairs laid over the entire 8 foot wall is no more than 10% of the nominal thickness (assuming the wall is perfectly flat).
ADCs are commonly integrated into a monolithic unit on one substrate of an integrated circuit (IC) or chip. Silicon, however, only allows up to about 10 bits of matching and is insufficient alone to achieve higher resolution. Correction and calibration techniques are known to improve the resolution, such as laser trimming or fuse blowing. Such post-processing techniques, however, must be performed on a part-by-part basis thereby unduly complicating and increasing cost of the manufacturing process. Also, such post-processing techniques operate under fixed conditions and do not correct for inaccuracies or changes due to temperature, aging and/or operating conditions. Integrated calibration techniques are also known and usually operate to measure error at the backend and apply a correction factor. Such calibration techniques are limited by quantization and are usually limited correction to one-half bit of resolution of the converter itself. Also, the calibration techniques are incorporated in silicon and thus subject to the same limitations of the target circuitry.
Many ADC techniques and architectures are known. Some of the early ones were used in the low resolution converters. Flash conversion is a classical technique where the input signal is compared to a reference voltage and the result is decoded into a digital word. The flash needs 2N comparators where N is the number of bits of resolution. As a result, the number of comparators and the power consumption exponentially increase with higher resolution. Although some improvements have been made, practical solutions are limited to about 8 bits of resolution to achieve optimum performance.
Pipeline converters behave similarly to flash converters except that there is a finite latency between the analog sample and the digital representation of the sample, which is dependent on the number of stages in the pipeline. The matching of the elements in the converter is limited to approximately 10 bits, beyond which some calibration of the components is required in any architecture. When the resolution is increased, the input stages have to be more accurate in resolving the input signal, which results in slower conversion speeds because of the settling time of the amplifier. Time interleaving of multiple pipeline converters has been demonstrated. This technique is limited by the accuracy of the sampling interval relative to the other stages, the relative gain and offset match, and the timing jitter of the sampling clocks
Successive approximation converters also allow higher resolutions but tend to be slower since they usually require N cycles to produce the answer. Sigma delta techniques allow much higher resolutions (10 to 24 bits), but are relatively slow since the requisite level resolution is achieved by oversampling the input signal and noise shaping. Folding is another high speed technique in which the signal is xe2x80x9cfoldedxe2x80x9d by using several folding amplifiers to replicate the input signal and by detecting zero crossings of the folding amplifiers to produce the digital output. Again, for higher resolution, the folding technique requires many folding amplifiers resulting in relatively high power consumption. Furthermore, the folding amplifiers must be faster by a factor that is equivalent to the folding ratio used in the converter. Higher resolution folding also requires calibration. Although interpolation, when used with folding, reduces the number of folding amplifiers, the resulting dynamic range of the converter is also limited.
An analog to digital converter (ADC) in accordance with embodiments of the present invention performs subranging and interpolation to convert an input analog signal into a stream of output digital values with a predetermined resolution. It is appreciated that an ADC according to at least one embodiment of the present invention may be implemented using a pipelined architecture with multiple sequential stages to resolve the digital value. The ADC may include, for example, a sampler that regularly samples an input analog signal and that provides a stream of sample signals to a first stage. The ADC further includes at least one secondary stage, where each secondary stage is coupled in sequential order after the first stage. The ADC also includes an error corrector or combiner that combines the digital results of the stages and generates a corresponding stream of digital values.
The first stage flash converts the stream of sample signals into corresponding primary multiple bit values and subranges a reference ladder for each primary multiple bit value into corresponding sets of reference signals. Each secondary stage is coupled in sequential order after the first stage. Each secondary stage amplifies each set of residual signals from a prior stage, interpolates each set of amplified residual signals using a resistive ladder, flash converts each set of amplified residual signals into corresponding secondary multiple bit values, and chooses the correct subrange of residual signals for each corresponding secondary multiple bit value. The final stage amplifies each set of residual signals from a prior stage and flash converts each set of amplified residual signals of the final stage into corresponding final multiple bit values.
The error corrector combines each primary multiple bit value with one or more corresponding secondary multiple bit values and a final multiple bit value into a corresponding stream of digital values representative of the analog signal. The error corrector may include an adder that adds each set of corresponding multiple bit values from most significant to least significant to determine a corresponding sum value. The error corrector further determines a corresponding digital value based on each sum value. The adder may be configured to align the most significant bit of each secondary and final multiple bit value with the least significant bit of a corresponding multiple bit value determined by an adjacent previous stage including the first stage. Also, the adder may discard at least one least significant bit of each sum value to determine a corresponding digital value.
The first stage may include a flash ladder, a first flash converter, a reference resistive ladder and first select logic. The flash ladder receives a reference voltage and provides a series of intermediate voltages. The first flash converter compares each sample signal with the series of intermediate voltages and decodes a resulting comparison into a corresponding primary multiple bit value. The reference resistive ladder receives the reference voltage and provides an interpolated series of reference voltages. The first select logic outputs a plurality of tap voltages within a selected subrange of the reference resistive ladder corresponding to each primary multiple bit value. The flash converter may include a plurality of amplifiers, a plurality of latches and a decoder. Each flash amplifier has one input coupled to a corresponding junction of the flash ladder and a second input receiving the stream of sample signals. Each latch is coupled to the output of a corresponding amplifier for latching a binary value. The decoder determines a binary transition for each sample signal and generates a corresponding primary multiple bit value indicative thereof. The first select logic and first flash converter may be collectively configured to select an overlap of tap voltages of the reference resistive ladder relative to the binary transition.
The sampler may include a first track and hold circuit that receives a clock signal, that tracks the analog signal for a first portion of the clock cycle and that holds a sample signal for the remaining portion of the clock cycle. The sampler may further include a second track and hold circuit that tracks each sample signal from the first track and hold circuit for the remaining portion of the clock cycle and that holds a second sample signal during the following portion of each clock cycle. In a practical ADC, the first track and hold circuit regularly samples the input analog signal and outputs a series of samples based on a clock signal. The clock signal is selected as approximately twice the requisite Nyquist rate for the input signal. In a specific embodiment, for example, the bandwidth of the input signal is 40 MHz and the clock signal is approximately 80 MHz. Each flash comparator uses a substantial portion of each clock cycle so that by the time the first set of preamplifiers need the sample for differential amplification, the track and hold circuit must track the input signal for the next sample. In the specific embodiment, a second track and hold circuit tracks the first sample while held by the first track and hold circuit, and then holds the sample at its output while the first circuit tracks the input signal. In this manner, the second track and hold circuit acts as a memory to maintain the sample for use by the preamplifiers.
A first secondary stage may include a plurality of first preamplifiers. Each preamplifier amplifies a difference between each second sample signal and each tap voltage of a corresponding selected subrange of the reference resistive ladder. Each secondary stage may include a plurality of preamplifiers, a resistive interpolation ladder, a flash converter and select logic. The preamplifiers are coupled to select logic of a prior stage and amplify a residual signal defined within a selected portion of a resistive ladder of the prior stage. The resistive interpolation ladder interpolates the amplified residual signals. The flash converter converts each set of amplified residual signals into a corresponding second multiple bit value. The select logic outputs a selected set of interpolated signals within a corresponding selected subrange of the resistive interpolation ladder for each corresponding second multiple bit value.
The secondary stage flash converters are configured in a similar manner as the first stage flash converter except that the amplifier inputs receive outputs from stage preamplifiers rather than a resistive ladder. A minor exception occurs when a preamplifier is completely removed for calibration in which one flash converter amplifier receives interpolated signals of an interpolation ladder driven by surrounding preamplifiers. Each amplifier and latch pair of each flash converter collectively operates as a comparator. The secondary stage select logic is configured to include an overlap for each selected portion of the resistive interpolation ladder. In one embodiment, the select logic includes a plurality of switches that select interpolative junctions between a selected sequential pair of the plurality of preamplifiers and that select an overlap including interpolative junctions on either side of the selected sequential pair. The amount of overlap may be half range on either side to ensure that the sampled signal is not lost due to comparator offsets and to provide 1 bit of digital redundancy used for digital correction.
In one embodiment, calibration circuitry is provided which calibrates the reference ladder, a first set of preamplifiers within a first secondary stage and a second set of preamplifiers within a second secondary stage. It is noted that the present invention is not limited to high accuracy converters and may be applied to converters used in most if not all ADC applications. The particular subranging, amplifying and interpolating pipeline architecture, however, facilitates accuracy especially when calibration is employed. In calibrated embodiments, the first flash ladder and each of the flash converters only need a modest level of accuracy and linearity. In the particular embodiment illustrated, calibration is performed periodically in the background and does not interrupt normal operation. The use of calibration and overlap selection ensures that signal being converted is not lost in the pipeline and provides digital redundancy for digital error correction. Digital values determined by the flash converters that appear to be incorrect are automatically corrected by the error correction circuitry using digital alignment and summation facilitated by the digital redundancy.
An ADC according to alternative embodiments of the present invention includes a track and hold circuit that samples an analog signal, a flash ladder, a first flash converter that uses the flash ladder and analog samples to generate a first set of bits, a reference resistive ladder having a plurality of tapped reference voltages, first select logic that selects a portion of the reference resistive ladder corresponding to the first set of bits, a first set of preamplifiers that amplifies a difference between each analog sample and each of the plurality of tapped voltages of the selected portion of the resistive reference ladder, a first interpolator resistive ladder that interpolates the outputs of the first set of amplifiers, a second flash converter that determines a second set of bits indicative of a zero-crossing of outputs of the first set of preamplifiers, second select logic that selects a plurality of tapped voltages within a portion of the first interpolator resistive ladder corresponding to the second set of bits, a second set of preamplifiers that amplifies a difference of each of the selected plurality of tapped voltages of the first interpolator resistive ladder, a third flash converter that determines a third set of bits indicative of a zero-crossing of outputs of the second set of preamplifiers, and a combiner that combines the first, second and third sets of bits to provide a digital value representative of the sample.
The ADC may further include a second interpolator resistive ladder that interpolates the outputs of the second set of amplifiers, third select logic that selects a plurality of tapped voltages within a portion of the second interpolator resistive ladder corresponding to the third set of bits, a third set of preamplifiers that amplifies a difference of each of the selected plurality of tapped voltages of the second interpolator resistive ladder, and a fourth flash converter that determines a fourth set of bits indicative of a zero-crossing of outputs of the third set of preamplifiers, where the combiner combines the first, second, third and fourth sets of bits to provide the digital output value representative of the sample.
The ADC may further include a third interpolator resistive ladder that interpolates the outputs of the third set of amplifiers, fourth select logic that selects a plurality of tapped voltages within a portion of the third interpolator resistive ladder corresponding to the fourth set of bits, a fourth set of preamplifiers that amplifies a difference of each of the selected plurality of tapped voltages of the third interpolator resistive ladder, and a fifth flash converter that determines a fifth set of bits indicative of a zero-crossing of outputs of the fourth set of preamplifiers, where the combiner combines the first, second, third, fourth and fifth sets of bits to provide the digital output value representative of the sample.
A method of converting an analog signal to a digital value in accordance with embodiments of the present invention includes regularly sampling the analog signal to provide a stream of sample signals, dividing a reference signal into a plurality of intermediate signals and separately into a plurality of reference signals, flash converting each sample signal with the intermediate signals to determine corresponding first binary values, selecting a subrange of the plurality of reference signals based on each first binary value, amplifying a difference between each sample signal and each reference signal of a corresponding selected subrange of reference signals to provide corresponding sets of first amplified residual signals, flash converting each set of first amplified residual signals to determine corresponding second binary values, interpolating each set of first amplified residual signals to provide corresponding sets of first interpolated signals, selecting a subrange of each set of first interpolated signals based on each second binary value, amplifying the subrange of signals of each set of first interpolated signals to provide corresponding sets of second amplified residual signals, flash converting each set of second amplified residual signals to determine corresponding third binary values, and combining corresponding sets of first, second and third binary values to generate a digital output value.
The flash converting may include comparing a plurality of differential signals, latching comparator results into a plurality of comparator values, decoding the comparator values to determine a binary transition point, and providing a binary value indicative of the transition point. The method may further include interpolating each set of second amplified residual signals to provide corresponding sets of second interpolated signals, selecting a subrange of signals of each set of second interpolated signals based on each third binary value, amplifying a subrange of signals of each set of second interpolated signals to provide corresponding sets of third amplified residual signals, and flash converting each set of third amplified residual signals to determine corresponding fourth binary values, where the combining involves combining corresponding sets of first, second, third and fourth binary values to generate the digital output value. The interpolating, selecting, amplifying and comparing may be repeated as often as necessary to provide additional sets of binary values used to generate the digital output value.
The combining may include aligning corresponding sets of binary values from most significant to least significant, and adding the aligned binary values to achieve a sum value. The aligning may include aligning the most significant bit of each next binary value with the least significant bit of a corresponding prior binary value. The method may further include discarding at least one least significant bit of the sum value to determine the output digital value.
Another method of converting an analog signal to a digital value in accordance with embodiments of the present invention includes sampling the analog signal, flash converting the analog sample with a first plurality of intermediate signals of a reference signal to determine a first binary value, dividing the reference signal to provide a plurality of accurate reference signals, subranging the plurality of accurate reference signals based on the first binary value, and amplifying a difference between the analog sample and subranged reference signals to provide amplified residual signals. The method further includes repeating each of the following flash converting, interpolating, subranging and amplifiying for the analog sample to determine a sufficient number of binary values to achieve a desired resolution. The repeated steps include flash converting the amplified residual signals to determine a subsequent binary value, interpolating the amplified residual signals, subranging the amplified residual signals based on the subsequent binary value, and amplifying the subranged amplified residual signals. The method also includes combining the determined binary values to determine the digital value.